1. Field of the Invention
The present invention is directed to the field of microprocessors, and more particularly, to alignment of clock signals in microprocessors.
2. Description of Related Art
Conventionally, many of the digital circuits that make up a microprocessor are synchronously designed to transfer a digital signal in accordance with a clock signal and, thus, require precise timing to function properly. To manage the timing requirements throughout the microprocessor, the microprocessor is typically divided up into several clock domains.
When a digital signal travels across two clock domains, the clock signals used within the two clock domains should be synchronized so that the data signal will be received in a specific window of time in order for it to be utilized by a receiving component. Typically, this specific window of time is defined in terms of set up and hold times which define a period of time during which a data signal must be stable to be correctly received, e.g., sampled.
The synchronization of two clock signals that is particularly important in a microprocessor is the synchronization of the central processor unit (CPU) clock signal and the address/data bus clock signal, such as a JBUS clock signal, as these clock signals control the flow of information between the CPU and elements peripheral to the CPU.
FIG. 1 illustrates a block diagram of a prior art circuit 100 used for generating a JBUS clock signal 118 utilizing a system clock signal 110 and a CPU clock signal 114. In circuit 100, system clock signal 110 was generated at a fixed frequency and was input to a phase lock loop (PLL) circuit 112 to generate a CPU clock signal 114. Unfortunately, generation of CPU clock signal 114 using PLL circuit 112 typically resulted in some static phase offset being introduced into CPU clock signal 114 due to current leakage in PLL circuit 112 as well as other well known problems inherent to PLL circuit 112.
Static phase offset, also known as phase error, is typically a measure of the time difference between the averaged input reference clock signal and the averaged feedback input signal when a PLL circuit is locked and the input reference frequency is stable. In prior art circuit 100, static phase offset measured the time difference between the averaged leading edge of system clock signal 110 and the averaged leading edge of CPU clock signal 114.
Although PLL circuit 112 typically utilized a feedback signal in the generation of CPU clock signal 114 to maintain synchronization, some static phase offset still remained and resulted in delay of the leading edge of CPU clock signal 114 with reference to the leading edge of system clock signal 110. Consequently, CPU clock signal 114 and system clock signal 110 were typically not synchronized, e.g., the leading edges were not in alignment, when they were input to an alignment detection circuit 116 used in generating JBUS clock signal 118.
In alignment detection circuit 116, system clock signal 110 and CPU clock signal 114 were used in generating JBUS clock signal 118. However, due to the static phase offset introduced by PLL circuit 112 into CPU clock signal 114, the leading edge of JBUS clock signal 118 was frequently generated with an adjustment back one or more clock cycles from where it should, under ideal conditions, have been aligned with CPU clock signal 114. Consequently, synchronization, e.g., alignment of the leading edges, of JBUS clock signal 118 to CPU clock signal 114 often became uncontrollable.
FIG. 2 illustrates an example of a timing diagram 200 for prior art circuit 100 including system clock signal 110, CPU clock signal 114, and resulting JBUS clock signal 118. Referring now to FIGS. 1 and 2 together, assume JBUS clock signal 118 was to be generated at a two clock cycle delay from system clock 110 which had a frequency fPA—SYS and was to be in alignment with the leading edge of CPU clock signal 114. When system clock signal 110 was input to PLL circuit 112, resulting CPU clock signal 114 was generated with a frequency fPA—CPU and had a non-synchronous leading edge due to a static phase offset 202 introduced by PLL circuit 112.
When system clock signal 110 and CPU clock signal 114 were input to alignment detection circuit 116, JBUS clock signal 118 was generated with a frequency fPA—JBUS that was equal to frequency fPA—SYS of system clock 110. However, rather than the leading edge of JBUS clock signal 118 being synchronized with the leading edge of CPU clock signal 114 at a two clock cycle delay from system clock 110, for example, clock cycle 3 (indicator A), the leading edge of JBUS clock signal 118 was generated with a misalignment 204, for example, to clock cycle 4 (indicator B).
In earlier generations of microprocessors, the static phase offset of CPU clock signal 114 was not a significant problem in the generation of JBUS clock signal 118 due to slower clock speeds, smaller leakage current, and comparatively larger timing tolerances. However, as clock speeds increased and component sizes decreased, timing tolerances became smaller, for example, smaller set up and hold times, and the static phase offset introduced into CPU clock signal 114 became excessive, and a more pronounced problem in generation of JBUS clock signal 118. The misalignment of the leading edge of JBUS clock signal 118 often resulted in set-up and hold time failures with consequent data loss.